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LTC1143L-ADJ Datasheet(PDF) 9 Page - Linear Technology

Part # LTC1143L-ADJ
Description  Dual High Efficiency SO-16 Step-Down Switching Regulator Controllers
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1143L-ADJ Datasheet(HTML) 9 Page - Linear Technology

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LTC1143/LTC1143L
LTC1143L-ADJ
APPLICATIONS INFORMATION
MAXIMUM OUTPUT CURRENT (A)
0
0.20
0.15
0.10
0.05
0
4
1143 F02
1
2
3
5
Figure 2. Selecting RSENSE
The load current below which Burst Mode operation
commences, IBURST, and the peak short circuit current,
ISC(PK), both track IMAX. Once RSENSE has been chosen,
IBURST and ISC(PK) can be predicted from the following:
IBURST
15mV
RSENSE
ISC(PK) =
150mV
RSENSE
The LTC1143 series automatically extends tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ISC(AVG) to be reduced to approximately IMAX.
L and CT Selection for Operating Frequency
Each regulator section of the LTC1143 series uses a
constant off-time architecture with tOFF determined by an
external timing capacitor CT. Each time the P-channel
MOSFET switch turns on the voltage on CT is reset to
approximately 3.3V. During the off-time, CT is discharged
by a current that is proportional to VOUT. The voltage on CT
is analogous to the current in inductor L, which likewise
decays at a rate proportional to VOUT. Thus the inductor
value must track the timing capacitor value.
The value of CT is calculated from the desired continuous
mode operating frequency:
C
f
VV
VV
T
IN
OUT
IN
D
=
+


1
13 10
4
.
where VD is the drop across the diode.
A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3.
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency of the circuit in Figure 1 is given by:
f
t
V
V
OFF
OUT
IN
≈−


1
1
where:
tC
V
V
OFF
T
REG
OUT
=


13 104
.
VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT
is the measured output voltage. Thus VREG/VOUT = 1 in
regulation.
Note that as VIN decreases, the frequency decreases.
When the input-to-output voltage differential drops below
1.5V for a particular section, the LTC1143 series reduces
tOFF in that section by increasing the discharge current in
CT. This prevents audible operation prior to dropout.
FREQUENCY (kHz)
0
50
100
150
200
LTC1143 F03
250
1000
800
600
400
200
0
300
VIN = 12V
VIN = 10V
VIN = 7V
VSENSE = VOUT = 5V
Figure 3. Timing Capacitor Value


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