8

LT1186F

AGND (Pin 5): This is the low current analog ground. It is

the negative sense terminal for the internal 1.24V refer-

Connect low current signal paths that terminate to ground

and frequency compensation components that terminate

to ground directly to this pin for best regulation and

performance.

SHDN (Pin 6): Pulling this pin low causes complete

regulator shutdown with quiescent current typically re-

duced to 35

µA. If the pin is not used, use a pull-up resistor

to force a logic high level (maximum of 6V) or tie directly

output current setting and returns to this level when the

logic-low signal at the shutdown pin is removed.

CLK (Pin 7): This pin is the shift clock for the DAC. This

clock synchronizes the serial data and is a Schmitt

trigger input. In standard SPI mode, the clock shifts data

of the clock respectively. In pulse mode, the rising edge

of the clock either increments or decrements the counter.

This action depends on the choice of a 1-wire interface

(increment only) or a 2-wire interface (increment/decre-

ment).

CS (Pin 8): This pin is the chip select input for the DAC. In

SPI mode, a logic low on the CS pin enables the DAC to

receive and transfer 8-bit serial data. After the serial input

data is shifted in, a rising edge of CS transfers the data into

up, a logic high places the DAC into pulse mode. Pulling CS

resets.

DAC. In SPI mode, the 8-bit serial data is shifted into the

ment-only mode and the pin function shifts to up or down

increment control of DAC output current. If UP/DN re-

ceives a logic-low signal, the counter configures to incre-

every falling edge of the clock. When CS rises high again,

DAC and provides an output current of 50

±3µA over

temperature. This pin can be biased from – 20V to 2V for

and provides the programming current which sets operat-

IC accepts an input voltage range of 3V minimum to 6.5V

maximum with little change in quiescent current (zero

switch current). An internal, low-dropout regulator pro-

vides a 2.4V supply for most of the internal circuitry.

Supply current increases as switch current increases at a

rate approximately 1/50 of switch current. This corre-

sponds to a forced Beta of 50 for the power switch. The IC

incorporates undervoltage lockout by sensing regulator

dropout and locking out switching for input voltages

below 2.5V. Hysteresis is not used to maximize the useful

range of input voltage. The typical input voltage is a 3.3V

or 5V logic supply.

ROYER (Pin 13): This pin connects to the center-tapped

primary of the Royer converter and is used with the BAT

pin in a floating-lamp configuration where lamp current is

controlled by sensing Royer primary-side converter cur-

rent. This pin is the inverting terminal of a high-side

current sense amplifier. The typical quiescent current is

50

µA into the pin. If the CCFL regulator is not used in a

floating-lamp configuration, tie the Royer and BAT pins

together.