 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LTC1235CN Datasheet(PDF) 11 Page - Linear Technology |
|
||||||||||||||||||||||||||||||
LTC1235CN Datasheet(HTML) 11 Page - Linear Technology |
|
|
11 / 16 page  11 LTC1235 S APPLICATI I FOR ATIO Table 1 shows the state of each pin during battery backup. If the backup battery is not used, connect VBATT to GND and VOUT to VCC. IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is +5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write input of battery-backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 6 shows the timing diagram of CE IN and CE OUT. CE IN can be derived from the microprocessor’s address decoder output. Figure 7 shows a typical nonvolatile CMOS RAM application. Figure 6. Timing Diagram for CE IN and CE OUT SIGNAL STATUS VCC C2 monitors VCC for active switchover. BACKUP BACKUP is ignored. VOUT VOUT is connected to VBATT through an internal PMOS switch. VBATT The supply current is 1 µA maximum. BATT ON Logic high. The open circuit output voltage is equal to VOUT. PFI Power Failure Input is ignored. PFO Logic low PB RST PB RST is ignored. RESET Logic low RESET Logic high. The open circuit output voltage is equal to VOUT. LOW LINE Logic low WDI Watchdog Input is ignored. WDO Logic high. The open circuit output voltage is equal to VOUT. CE IN Chip Enable Input is ignored. CE OUT Logic high. The open circuit output voltage is equal to VOUT. Table 1. Input and Output Status in Battery Backup Mode Memory Protection The LTC1235 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two pins, CE +5V +3V 0.1µF 10µF VBATT VCC LTC1235 VOUT GND LTC1235 F06 VCC RESET CE IN CE OUT BACKUP 0.1µF TO µP FROM DECODER CS 20ns PROPAGATION DELAY 62512 RAM + GND Figure 7. A Typical Nonvolatile CMOS RAM Application VCC V1 CE IN VOUT = VBATT VOUT = VBATT V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS LTC1235 F06 CE OUT BACKUP = VCC |
Similar Part No. - LTC1235CN |
|
Similar Description - LTC1235CN |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
