9

LTC1096/LTC1096L

LTC1098/LTC1098L

0

3

4

5

8

LTC1096/98 • TPC12

2

1

0

2

4

6

10

Digital Input Logic Threshold

vs Supply Voltage

Maximum Clock Frequency vs

Supply Voltage

Maximum Clock Frequency vs

Source Resistance

SUPPLY VOLTAGE (V)

0

0

0.25

0.5

0.75

1.0

1.25

1.5

246

8

LTC1096/98 • TPC11

10

1

0

0.25

0.50

1

10

100

LTC1096/98 • TPC10

0.75

+ INPUT

– INPUT

–

Wake-Up Time vs Supply Voltage

0

3

4

8

LTC1096/98 • TPC13

2

1

0

2

4

6

10

1

0

2.5

5.0

10

10

100

LTC1096/98 • TPC14

7.5

+

–

+

Minimum Wake-Up Time

vs Source Resistance

TEMPERATURE (°C)

–60

10

100

1000

100

LTC1096/98 • TPC15

1

0.1

0.01

–20

20

60

140

–40

0

40

80

120

ON CHANNEL

OFF CHANNEL

Input Channel Leakage Current

vs Temperature

Minimum Clock Frequency for

0.1LSB Error

ENOBs vs Frequency

FFT Plot

FREQUENCY (kHz)

1

0

2

4

6

8

10

10

100

LTC1096/98 • TPC17

9

7

5

3

1

TEMPERATURE (

°C)

–60

120

160

200

100

LTC1096/98 • TPC16

60

40

0

–20

20

60

140

–40

0

40

80

120

180

140

100

80

20

FREQUENCY (kHz)

0

–100

–90

–70

–60

–50

0

–30

2

4

LTC1096/98 • TPC18

–80

–20

–10

–40

6

8

10

12

14

16

* Maximum CLK frequency represents the clock frequency at which a 0.1LSB shift in the error at any code

transition from its 0.75MHz value is first detected.

∆error ≤ 0.1LSB) represents

the frequency at which a 0.1LSB shift in any code transition from its 500kHz value is first detected.

CC

HARA TERISTICS

A

TYPICALPERFOR

CE