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LTC4229 Datasheet(PDF) 10 Page - Linear Technology

Part # LTC4229
Description  Ideal Diode and Hot Swap Controller
Download  28 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4229 Datasheet(HTML) 10 Page - Linear Technology

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LTC4229
10
4229f
For more information www.linear.com/LTC4229
operaTion
The LTC4229 functions as an ideal diode with inrush cur-
rent limiting and overcurrent protection. It controls two
external N-channel MOSFETs on a supply path, a diode
MOSFET (MD) and a Hot Swap MOSFET (MH).
When the LTC4229 is first powered up, the gates of the
external MOSFETs are held low, keeping them off. The gate
drive amplifier (GD) monitors the voltage between the IN
and DSNS pins and drives the DGATE pin. The amplifier
quickly pulls up the DGATE pin, turning on the MOSFET for
ideal diode control, when it senses a large forward voltage
drop. An external capacitor connected between the CPO
and DSRC pins provides the charge needed to quickly
turn on the ideal diode MOSFET. An internal charge pump
charges up this capacitor at device power-up. The DGATE
pin sources current from the CPO pin and sinks current
into the DSRC and GND pins. When the DGATE to DSRC
voltage exceeds 0.7V, the DSTAT pin pulls low to indicate
that the ideal diode MOSFET is turned on.
If the LTC4229 is out of undervoltage and overvoltage
conditions, pulling the EN pin low initiates a debounce
timing cycle that can be a fixed 100ms or adjustable delay
as configured at the DTMR pin. After this timing cycle, a
10µA current source from the charge pump ramps up
the HGATE pin. When the Hot Swap MOSFET turns on,
the inrush current is limited at a level set by an external
sense resistor (RS) connected between the SENSE+ and
SENSEpins. An active current limit amplifier (CL) servos
the gate of the MOSFET to 25mV or less across the cur-
rent sense resistor depending on the voltage at the FB
pin. Inrush current can be further reduced, if desired, by
adding a capacitor from HGATE to GND. When FB voltage
rises above 1.235V and the MOSFET’s gate drive (HGATE
to OUT voltage) exceeds 4.2V, the PWRGD pin pulls low.
When both of the MOSFETs are turned on, the gate drive
amplifier controls DGATE to servo the forward voltage
drop (VIN – VDSNS) across the sense resistor and the two
MOSFETs to 50mV if DSNS and OUT pins are connected
together. If the load current causes more than 50mV of
voltage drop, the DGATE voltage rises to enhance the
MOSFET used for ideal diode control. For large output
currents, the ideal diode MOSFET is driven fully on and the
voltagedropacrosstheMOSFETsisequaltothesumofthe
ILOAD • RDS(ON) of the two MOSFETs in series. However, if
DSNS and SENSE+ pins are connected together, the gate
drive amplifier attempts to regulate 50mV across the ideal
diode MOSFET only regardless of the ILOAD • RDS(ON) drop
across the Hot Swap MOSFET.
In the case of an input supply short circuit when the MOS-
FETs are conducting, a large reverse current starts flowing
from the load towards the input. The gate drive amplifier
detects this failure condition and turns off the ideal diode
MOSFET by pulling down the DGATE pin.
Inthecasewhereanovercurrentfaultoccursonthesupply
output, the current is limited with foldback. After a delay
set by 100µA charging the FTMR pin capacitor, the fault
filter times out and pulls the HGATE pin low, turning off
the Hot Swap MOSFET. The FAULT pin is also latched low.
At this point, the DGATE pin continues to pull high and
keeps the ideal diode MOSFET on.
Internal clamps limit both the DGATE to DSRC and CPO to
DSRCvoltagesto12V.ThesameclampsalsolimittheCPO
and DGATE pins to a diode voltage below the DSRC pin.
Another internal clamp limits the HGATE to OUT voltage
to 12V and also clamps the HGATE pin to a diode voltage
below the OUT pin.
Power to the LTC4229 is supplied from either the IN,
SENSE+ or OUT pins, through an internal diode-OR circuit
to a low dropout regulator (LDO). That LDO generates a
5V supply at the INTVCC pin and powers the LTC4229’s
internal low voltage circuitry


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