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RFMD2081

DS140110

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Theory of Operation

The RFMD2081 is a wideband IQ modulator with integrated fractional-N synthesizer and a low noise VCO core. It features a

high accuracy LO quadrature divider followed by buffer circuits which drive the I and Q mixers of the modulator with the quadra-

ture LO signals. The RFMD2081 has an integrated voltage reference and low drop out regulators supplying critical circuit

blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control are achieved through a

mixture of hardware and software controls. All on-chip registers are programmed through a simple three-wire serial interface.

VCO

The VCO core in the RFMD2081 consists of three VCOs which, in conjunction with the integrated LO dividers of /1 to /32, cover

the frequency range of 90MHz to 5400MHz. The modulator quadrature divider provides a further fixed divide by two to give the

center frequency range at the modulator output of 45MHz to 2700MHz.

Each VCO has 128 overlapping bands which are used to achieve low VCO gain and optimal phase noise performance across

the whole tuning range. The chip automatically selects the correct VCO (VCO auto-select) and the correct VCO band (VCO

coarse tuning) to generate the desired LO frequency based on the values programmed into the PLL1 and PLL2 registers banks.

The VCO auto-select and VCO coarse tuning are triggered every time ENBL is taken high, or if the PLL re-lock self clearing bit is

programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the

band selection process fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is

oscillating at approximately the correct frequency. The output of this band selection, CT_CAL, is made available in the read-

back register. A value of 127 or 0 in this register indicates that the coarse tuning was unsuccessful, and this should also be

indicated by the CT_FAILED flag also available in the read-back register. A value between 1 and 126 indicates a successful cal-

ibration, the actual value being dependent on the desired frequency as well as process variation for a particular device.

The band select process will center the VCO tuning voltage at about 0.8V, compensating for manufacturing tolerances and pro-

cess variation as well as environmental factors including temperature. In applications where the device is left enabled at the

same LO frequency for some time it is recommended that automatic band selection be performed for every 30°C change in

temperature. This assumes an active loop filter.

The RFMD2081 features a differential LO input to allow the mixer to be driven from an external LO source. The fractional-N PLL

can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in some applications.

This may also require an external op-amp, dependant on the tuning voltage required by the external VCO.

Fractional-N PLL

The RFMD2081 contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL

includes automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable

loop response and phase noise performance. As well as the VCO auto-select and coarse tuning, there is a loop filter calibration

mechanism which can be enabled if required. This operates by adjusting the charge pump current to maintain loop bandwidth.

This can be useful for applications where the LO is tuned over a wide frequency range.

The PLL has been designed to use a reference frequency of between 10MHz and 104MHz from an external source, which is

typically a temperature controlled crystal oscillator (TCXO). A reference divider (divide by 1 to divide by 7) is supplied and

should be programmed to limit the frequency at the phase detector to a maximum of 52MHz.

Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the

label PLL2. The active register bank is selected by the state of the MODE pin, low for PLL1 and high for PLL2.

The VCO outputs are first divided down in a high frequency prescalar. The output of this high frequency prescalar then enters

the N divider, which is a fractional divider containing a dual-modulus prescalar and a digitally spur-compensated fractional

sequence generator. This allows very fine frequency steps and minimizes fractional spurs. The fractional energy is randomized

and appears as fractional noise at frequency offsets above 100kHz which will be attenuated by the loop filter. An external loop

filter is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time for example.