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AN95089 Datasheet(PDF) 8 Page - Ramtron International Corporation |
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AN95089 Datasheet(HTML) 8 Page - Ramtron International Corporation |
8 / 19 page PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques www.cypress.com Document No. 001-95089 Rev. *A 8 Decimal Value of Bits 6-0 Capacitance Value C2 0 3.6900 pF 1 3.7911 pF 2 3.8922 pF ……. …….. 127 16.428 pF Bit 7 is used for coarse control of the capacitance value at the XO node. Bit 7 = 0 means that no additional capacitance is turned ON at the XO node. Bit 7 = 1 means that an additional capacitance of 8.1 pF is turned ON at the XO node. CL and Clock Accuracy Changes in C1 and C2 result in a change in CL. Therefore, both values should be changed to tune the crystal properly. Even though there is no one-to-one look-up table to relate a change in capacitance value to a change in the ppm accuracy, a general practice is mentioned below: If the ppm is negative (i.e., the measured frequency is less than 24 MHz), then decrease the capacitance trim value on XI and XO because a smaller CL value results in an increase in fp according to Equation 2 If the ppm is positive (i.e., the measured frequency is more than 24 MHz), then increase the trim capacitance value because a larger CL value results in a decrease in fp according to Equation 2: For optimal phase noise, the total capacitance on the XI pin should be 0.8 times the total capacitance on the XO pin. 5 Is Tuning Required for Each Board? Table 1 and Figure 6 show the ppm variation measured for the same load cap value on 14 boards with the same PCB layout after tuning the CL for one board. Table 1. ppm Variation Across Boards for the Same CL Board Measured Frequency ppm 1 23999998 -0.08 2 23999912 -3.66 3 24000051 2.12 4 23999859 -5.87 5 23999965 -1.45 6 23999912 -3.66 7 23999840 -6.66 8 24000064 2.66 9 23999951 -2.04 10 23999968 -1.33 11 24000000 0 12 24000061 2.54 13 23999800 -8.33 14 23999867 -5.54 |
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