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M14D1G1664A-2S Datasheet(PDF) 11 Page - Elite Semiconductor Memory Technology Inc.

Part # M14D1G1664A-2S
Description  Internal pipelined double-data-rate architecture; two data access per clock cycle
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M14D1G1664A-2S Datasheet(HTML) 11 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
(Preliminary)
M14D1G1664A (2S)
Automotive Grade
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 0.1
11/65
AC Timing Parameter & Specifications
-1.8
Parameter
Symbol
Min.
Max.
Unit
Note
CL=7
tCK (avg)
1875
7500
ps
13
CL=6
tCK (avg)
1875
7500
ps
13
CL=5
tCK (avg)
2500
7500
ps
13
Clock period
CL=4
tCK (avg)
3000
7500
ps
13
DQ output access time from
CLK/ CLK
tAC
-350
+350
ps
10
CLK high-level width
tCH (avg)
0.48
0.52
tCK (avg)
13
CLK low-level width
tCL (avg)
0.48
0.52
tCK (avg)
13
DQS output access time from
CLK/ CLK
tDQSCK
-325
+325
ps
10
Clock to first rising edge of DQS
delay
tDQSS
-0.25
+0.25
tCK (avg)
Data-in and DM setup time
(to DQS)
tDS
(base)
0
ps
4
Data-in and DM hold time
(to DQS)
tDH
(base)
75
ps
5
DQ and DM input pulse width
(for each input)
tDIPW
0.35
tCK (avg)
Address and Control Input
setup time
tIS (base)
125
ps
4
Address and Control Input hold
time
tIH (base)
200
ps
5
Control and Address input pulse
width
tIPW
0.6
tCK (avg)
DQS input high pulse width
tDQSH
0.35
tCK (avg)
DQS input low pulse width
tDQSL
0.35
tCK (avg)
DQS falling edge to CLK rising
setup time
tDSS
0.2
tCK (avg)
DQS falling edge from CLK
rising hold time
tDSH
0.2
tCK (avg)
Data strobe edge to output data
edge
tDQSQ
175
ps
Data-out high-impedance
window from CLK/ CLK
tHZ
tAC(max.)
ps
10
Data-out low-impedance window
from CLK/ CLK
tLZ
(DQS)
tAC(min.)
tAC(max.)
ps
10
DQ low-impedance window from
CLK/ CLK
tLZ
(DQ)
2 x tAC(min.)
tAC(max.)
ps
10
Half clock period
tHP
Min
(tCL(abs),tCH(abs))
ps
6,13


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