Fault-Protected, 12-Bit ADCs

with Software-Selectable Input Range

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5

TIMING CHARACTERISTICS

PARAMETERS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIN to SCLK Setup

100

ns

DIN to SCLK Hold

0ns

SCLK Fall to Output Data Valid

20

250

ns

CS Fall to Output Enable

100

ns

CS Rise to Output Disable

100

ns

CS to SCLK Rise Setup

100

ns

CS to SCLK Rise Hold

0ns

SCLK Pulse Width High

200

ns

SCLK Pulse Width Low

200

ns

rejection test.

Note 2: Offset error nulled. The ideal last-code transition is (FS - 1.5 LSB).

Note 3: PSRR measured at full scale. Tested at ±10V (MAX1272) and ±4.096V (MAX1273) input ranges.

Note 4: Acquisition and conversion times are dependent on the clock speed.

Typical Operating Characteristics

CONVERTING SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

5.20

5.15

5.05 5.10

4.85 4.90 4.95 5.00

4.80

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0

4.75

5.25

INTERNAL

REFERENCE

EXTERNAL

REFERENCE

CONVERTING SUPPLY CURRENT

vs. TEMPERATURE

TEMPERATURE (

°C)

60

35

-15

10

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0

-40

85

INTERNAL

REFERENCE

EXTERNAL

REFERENCE

STANDBY SUPPLY CURRENT

vs. TEMPERATURE

TEMPERATURE (

°C)

60

35

10

-15

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

-40

85

INTERNAL

REFERENCE

EXTERNAL

REFERENCE