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MAX1239KEEE Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX1239KEEE Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 22 page 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs 4 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF = 4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS MAX1237/MAX1239 2.7 3.6 Supply Voltage VDD MAX1236/MAX1238 4.5 5.5 V Internal reference 900 1150 fSAMPLE = 94.4ksps external clock External reference 670 900 Internal reference 530 fSAMPLE = 40ksps internal clock External reference 230 Internal reference 380 fSAMPLE = 10ksps internal clock External reference 60 Internal reference 330 fSAMPLE =1ksps internal clock External reference 6 Supply Current IDD Shutdown (internal REF off) 0.5 10 µA Power-Supply Rejection Ratio PSRR Full-scale input (Note 9) ±0.5 ±0.2 LSB/V TIMING CHARACTERISTICS (Figure 1) (VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF = 4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS FOR FAST MODE Serial-Clock Frequency fSCL 400 kHz Bus Free Time Between a STOP (P) and a START (S) Condition tBUF 1.3 µs Hold Time for START (S) Condition tHD, STA 0.6 µs Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition (Sr) tSU, STA 0.6 µs Data Hold Time (Note 10) tHD, DAT 0 900 ns Data Setup Time tSU, DAT 100 ns Rise Time of Both SDA and SCL Signals, Receiving tR Measured from 0.3VDD - 0.7VDD 20 + 0.1CB 300 ns Fall Time of SDA Transmitting tF Measured from 0.3VDD - 0.7VDD 20 + 0.1CB 300 ns Setup Time for STOP (P) Condition tSU, STO 0.6 µs Capacitive Load for Each Bus Line CB 400 pF Pulse Width of Spike Suppressed tSP 50 ns |
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