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MAX1289EKA-T Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX1289EKA-T Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 15 page edges. DOUT transitions on SCLK’s falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the µP on SCLK’s rising edge. SPI and MICROWIRE Interface When using an SPI (Figure 8a) or MICROWIRE inter- face (Figures 8a and 8b), set CPOL = CPHA = 0. Two 8-bit readings are necessary to obtain the entire 12-bit result from the ADC. DOUT data transitions on the seri- al clock’s falling edge and is clocked into the µP on SCLK’s rising edge. The first 8-bit data stream contains the first 8-bits of DOUT starting with the MSB. The sec- ond 8-bit data stream contains the remaining four result bits. DOUT then goes high impedance. QSPI Interface Using the high-speed QSPI interface (Figure 9a) with CPOL = 0 and CPHA = 0, the MAX1286–MAX1289 support a maximum fSCLK of 8MHz. One 12- to 16-bit reading is necessary to obtain the entire 12-bit result from the ADC. DOUT data transitions on the serial clock’s falling edge and is clocked into the µP on SCLK’s rising edge. The first 12 bits are the data. DOUT then goes high impedance (Figure 9b). PIC16 and SSP Module and PIC17 Interface The MAX1286–MAX1289 are compatible with a PIC16/PIC17 µC, using the synchronous serial port (SSP) module To establish SPI communication, connect the controller as shown in Figure 10a and configure the PIC16/PIC17 as system master. This is done by initializing its syn- chronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 1 and 2. In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to be synchronously transmitted and received simulta- neously. Two consecutive 8-bit readings (Figure 10b) are necessary to obtain the entire 12-bit result from the ADC. DOUT data transitions on the serial clock’s falling edge and is clocked into the µC on SCLK’s rising edge. The first 8-bit data stream contains the first 8 data bits starting with the MSB. The second data stream con- tains the remaining bits, D3 through D0. 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 ______________________________________________________________________________________ 11 Figure 8a. SPI Connections Figure 8b. MICROWIRE Connections CNVST SCLK DOUT I/O SCK MISO VDD SS SPI MAX1286– MAX1289 MAX1286– MAX1289 CNVST SCLK DOUT I/O SK SI MICROWIRE Table 1. Detailed SSPCON Register Content CONTROL BIT MAX1286–MAX1289 SETTINGS SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON) WCOL Bit 7 X Write Collision Detection Bit SSPOV Bit 6 X Receive Overflow Detect Bit SSPEN Bit 5 1 Synchronous Serial Port Enable Bit: 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins. CKP Bit 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection. SSPM3 Bit 3 0 SSPM2 Bit 2 0 SSPM1 Bit 1 0 SSPM0 Bit 0 1 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects FCLK = fOSC / 16. |
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