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MAX1247BEEE Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # MAX1247BEEE
Description  2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1247BEEE Datasheet(HTML) 5 Page - Maxim Integrated Products

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+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
_______________________________________________________________________________________
5
Figure 1
__________________________________________Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
0.5
0
1024
2048
3072
4096
INTEGRAL NONLINEARITY
vs. CODE
0.3
-0.3
-0.5
-0.1
0.1
0.4
0.2
-0.4
-0.2
0
CODE
0.50
0.00
2.25
2.75
4.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
VDD (V)
3.75
5.25
3.25
4.75
MAX1246
MAX1247
0.00
0.10
0.20
0.30
0.40
0.50
0.05
0.15
0.25
0.35
0.45
-60
-20
20
60
100
140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (°C)
MAX1247
MAX1246
VDD = 2.7V
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1246); VDD = +2.7V to +5.25V (MAX1247); TA = TMIN to TMAX; unless otherwise noted.)
Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX1246—internal reference, offset nulled; MAX1247—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Guaranteed by design. Not subject to production testing.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10: Measured as
|VFS(2.7V) - VFS(VDD, MAX)|.
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
Figure 1
Figure 2
Figure 1
MAX124_ _C/E
CONDITIONS
MAX124_ _M
ns
20
240
Figure 1
ns
tCSH
ns
240
tSTR
CS Rise to SSTRB Output Disable
ns
240
tSDV
CS Fall to SSTRB Output Enable
240
tSSTRB
SCLK Fall to SSTRB
ns
200
tCL
SCLK Pulse Width Low
ns
200
SCLK Pulse Width High
ns
0
CS to SCLK Rise Hold
ns
100
tCSS
CS to SCLK Rise Setup
ns
240
tTR
CS Rise to Output Disable
ns
240
tDV
CS Fall to Output Enable
tCH
20
200
tDO
SCLK Fall to Output Data Valid
ns
0
tDH
DIN to SCLK Hold
ns
µs
1.5
tACQ
Acquisition Time
0
tSCK
SSTRB Rise to SCLK Rise
ns
100
tDS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER


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