265ksps, +3V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

4

_______________________________________________________________________________________

20

70

ns

RD Rise to Output Disable

WR to CLK Fall Setup Time

40

ns

ns

CLK Pulse Width High

ns

CLK Period

40

RD Fall to Output Data Valid

20

70

ns

RD Fall to INT High Delay

100

ns

CS Fall to Output Data Valid

110

ns

208

CLK Pulse Width Low

40

ns

Data Valid to WR Rise Time

40

ns

WR Rise to Data Valid Hold Time

0

ns

CLK Fall to WR Hold Time

40

ns

CS to CLK or WR Setup Time

60

ns

CLK or WR to CS Hold Time

0

ns

CS Pulse Width

100

ns

WR Pulse Width (Note 8)

60

ns

20

100

ns

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

CS Rise to Output Disable

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have

been removed.

Note 3: Offset nulled.

Note 4: On channel is grounded; sine wave applied to off channels.

Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.

TIMING CHARACTERISTICS

6k

GND

GND

3k

DOUT

DOUT

20pF

20pF

Figure 1. Load Circuits for Enable/Disable Times