Multi-Range (±10V, ±5V, +10V, +5V),

Single +5V, 12-Bit DAS with 8+4 Bus Interface

_______________________________________________________________________________________

5

Note 1:

Rejection test. Tested for the ±10V input range.

Note 2:

Note 3:

Ground "on" channel; sine wave applied to all "off" channels.

Note 4:

Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.

Note 5:

Guaranteed by design. Not tested.

Note 6:

Use static loads only.

Note 7:

Tested using internal reference.

Note 8:

PSRR measured at full-scale.

Note 9:

External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD

= high control byte.

Note 10: Not subject to production testing. Provided for design guidance only.

or 2.4V.

TIMING CHARACTERISTICS

(Note 13)

ns

70

CONDITIONS

RD High to Output Disable

ns

120

RD Low to INT High Delay

ns

80

CS Pulse Width

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

ns

80

WR Pulse Width

ns

0

ns

0

CS to WR Hold Time

CS to WR Setup Time

ns

0

ns

0

CS to RD Hold Time

CS to RD Setup Time

ns

100

ns

50

CLK to WR Hold Time

CLK to WR Setup Time

ns

60

ns

0

Data Valid to WR Hold

Data Valid to WR Setup

ns

120

ns

120

HBEN High or HBEN Low to

Output Valid

RD Low to Output Data Valid