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MAX197BMYI Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX197BMYI Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 16 page Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface _______________________________________________________________________________________ 5 Note 1: Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the ±10V input range. Note 2: External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB. Note 3: Ground "on" channel; sine wave applied to all "off" channels. Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz. Note 5: Guaranteed by design. Not tested. Note 6: Use static loads only. Note 7: Tested using internal reference. Note 8: PSRR measured at full-scale. Note 9: External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD = high control byte. Note 10: Not subject to production testing. Provided for design guidance only. Note 11: All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V. Note 12: tDO and tDO1 are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V. Note 13: tTR is defined as the time required for the data lines to change by 0.5V. TIMING CHARACTERISTICS (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) (Note 13) ns 70 CONDITIONS tTR RD High to Output Disable ns 120 tINT1 RD Low to INT High Delay ns 80 tCS CS Pulse Width UNITS MIN TYP MAX SYMBOL PARAMETER ns 80 tWR WR Pulse Width ns 0 tCSWS ns 0 tCSWH CS to WR Hold Time CS to WR Setup Time ns 0 tCSRS ns 0 tCSRH CS to RD Hold Time CS to RD Setup Time ns 100 tCWS ns 50 tCWH CLK to WR Hold Time CLK to WR Setup Time ns 60 tDS ns 0 tDH Data Valid to WR Hold Data Valid to WR Setup Figure 2, CL = 100pF (Note 12) Figure 2, CL = 100pF (Note 12) ns 120 tDO ns 120 tDO1 HBEN High or HBEN Low to Output Valid RD Low to Output Data Valid |
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