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MAX196BENI Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX196BENI Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 16 page Clock Modes The MAX196/MAX198 operate with either an internal or an external clock. Control bits (D6, D7) select either internal or external clock mode. Once the desired clock mode is selected, changing these bits to program power-down will not affect the clock mode. In each mode, internal or external acquisition can be used. At power-up, external clock mode is selected. Internal Clock Mode Select internal clock mode to free the µP from the burden of running the SAR conversion clock. To select this mode, write the control byte with D7 = 0 and D6 = 1. A 100pF capacitor between the CLK pin and ground sets this frequency to 1.56MHz nominal. Figure 7 shows a linear relationship between the internal clock period and the value of the external capacitor used. External Clock Mode Select external clock mode by writing the control byte with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR timing relationships in internal and external acquisition modes, with an external clock. A 100kHz to 2.0MHz external clock with 45% to 55% duty cycle is required for proper operation. Operating at clock frequencies lower than 100kHz will cause a voltage droop across the hold capacitor, and subsequently degrade performance. Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface ______________________________________________________________________________________ 11 tCS tCSWS tWR tACQI tCONV tDH tDS tINT1 tD0 tTR tCSHW tCSRS tCSRH ACQMOD = "1" CS WR D7–D0 INT RD DOUT ACQMOD = "0" DATA VALID CONTROL BYTE CONTROL BYTE Figure 6. Conversion Timing Using External Acquisition Mode 2000 0 0 50 250 350 500 CLOCK PIN CAPACITANCE (pF) 100 150 200 300 1500 1000 Figure 7. Internal Clock Period vs. Clock Pin Capacitance |
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