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MAX199BMYI Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX199BMYI Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 16 page Multi-Range (±4V, ±2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface _______________________________________________________________________________________ 7 ______________________________________________________________Pin Description Digital Ground DGND 28 +5V Supply. Bypass with 0.1µF capacitor to AGND. VDD 27 INT goes low when conversion is complete and output data is ready. INT 24 Bandgap Voltage-Reference Output / External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect to VDD when using an external reference at the REF pin. REFADJ 25 Reference Buffer Output / ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. REF 26 Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high). D2/D10 12 Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high). D1/D9 13 Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB. D0/D8 14 Analog Ground AGND 15 Analog Input Channels CH0–CH7 16–23 Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus; when low, the 8 LSBs are available on the bus. HBEN 5 Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low. SHDN 6 Three-State Digital I/O D7–D4 7–10 Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high). D3/D11 11 When CS is low, a falling edge on RD will enable a read operation on the data bus. RD 4 When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle. WR 3 PIN Chip Select, active low. CS 2 Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode, place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical with CCLK = 100pF. CLK 1 FUNCTION NAME 100k 510k 24k REFADJ +5V 0.01 µF MAX199 Figure 1. Reference-Adjust Circuit 3k 3k DOUT DOUT +5V a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL CLOAD CLOAD Figure 2. Load Circuits for Enable Time |
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