74AUP2G240

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© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 8 — 24 January 2013

2 of 25

NXP Semiconductors

74AUP2G240

Low-power dual inverting buffer/line driver; 3-state

3.

Ordering information

4.

Marking

[1]

The pin 1 indicator is located on the lower left corner of the device, below the marking code.

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74AUP2G240DC

40 C to +125 C

VSSOP8

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74AUP2G240GT

40 C to +125 C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1

 1.95  0.5 mm

SOT833-1

74AUP2G240GF

40 C to +125 C

XSON8

extremely thin small outline package; no leads;

8 terminals; body 1.35

 1  0.5 mm

SOT1089

74AUP2G240GD

40 Cto +125 C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 3

 2  0.5 mm

SOT996-2

74AUP2G240GM

40 C to +125 C

XQFN8

plastic, extremely thin quad flat package; no leads;

8 terminals; body 1.6

 1.6  0.5 mm

SOT902-2

74AUP2G240GN

40 C to +125 C

XSON8

extremely thin small outline package; no leads;

8 terminals; body 1.2

 1.0  0.35 mm

SOT1116

74AUP2G240GS

40 C to +125 C

XSON8

extremely thin small outline package; no leads;

8 terminals; body 1.35

 1.0  0.35 mm

SOT1203

Table 2.

Marking codes

Type number

Marking code[1]

74AUP2G240DC

p40

74AUP2G240GT

p40

74AUP2G240GF

p2

74AUP2G240GD

p40

74AUP2G240GM

p40

74AUP2G240GN

p2

74AUP2G240GS

p2