Multirange, Single +5V, 12-Bit DAS

with 12-Bit Bus Interface

_______________________________________________________________________________________

5

Note 1:

Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.

Note 2:

Note 3:

Ground “on” channel; sine wave applied to all “off” channels.

Note 4:

Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.

Note 5:

Guaranteed by design. Not tested.

Note 6:

Use static loads only.

Note 7:

Tested using internal reference.

Note 8:

PSRR measured at full-scale.

Note 9:

External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD

= high control byte.

Note 10: Not subject to production testing. Provided for design guidance only.

TIMING CHARACTERISTICS

ELECTRICAL CHARACTERISTICS (continued)

Three-State Output Capacitance

15

pF

(Note 5)

Output High Voltage

V

Output Low Voltage

0.4

V

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

DIGITAL OUTPUTS (D11–D0, INT)

RD Low to Output Data Valid

120

ns

Data Valid to WR Setup

Data Valid to WR Hold

0

ns

60

ns

CLK to WR Setup Time

CLK to WR Hold Time

50

ns

100

ns

CS to RD Setup Time

CS to RD Hold Time

0

ns

0

ns

CS to WR Setup Time

CS to WR Hold Time

0

ns

0

ns

WR Pulse Width

80

ns

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CS Pulse Width

80

ns

RD Low to INT High Delay

120

ns

RD High to Output Disable

CONDITIONS

70

ns

(Note 13)