dBm

2.5GHz, +20dBm Power Amplifier IC

in UCSP Package

_______________________________________________________________________________________

3

AC ELECTRICAL CHARACTERISTICS

All power levels set by D0, D1;

any load phase angle, any duration

All power levels set by D0, D1; load VSWR

≤ 3:1

SHDN = 1 to 0, D0 = D1 = logic high-to-low transition

CONDITIONS

6:1

Maximum Output VSWR Without

Damage (Note 8)

dB

45

Input to Output Isolation in

Shutdown

dBm

-30

Nonharmonic Spurious Output

(Note 9)

µs

2

Power Ramp Turn-Off Time

(Notes 7, 9)

UNITS

MIN

TYP

MAX

PARAMETERS

26

8

Power Control Steps

(Notes 4, 9)

SHDN = 0 to 1, D0 = D1 = logic low-to-high transition

µs

2

Power Ramp Turn-On Time

(Notes 6, 9)

dBm

-15

-5

Harmonic Output (Notes 3, 9)

dBm

1.5:1

2:1

In-Band Spurious Noise

(Notes 5, 9)

Frequency offset = ±550kHz

dBc

-21

-20

Frequency offset = ±1.5MHz

dBm

-20

Frequency offset = ±2.5MHz

-40

Input VSWR (Note 9)

dB

2

8.6

design and characterization but are not production tested.

Note 2: Supply current is measured with RF power applied to the input.

Note 3: Measured with an output-matching network to minimize the 2nd and 3rd harmonics (see Applications section).

Note 4: Power steps between adjacent power levels. All other operating conditions remain constant during power step change.

Note 5: Output measured in 100kHz RBW. Test signal modulation shall comply with GFSK, BT = 0.5, 1-bit/symbol, 1Mbps, frequency

deviation = 175kHz.

Note 6: The total turn-on time for the PA output power to settle within 1dB of the final value.

Note 7: The total turn-off time for the PA output power to drop to -10dBm.

Note 8: After removal of the load mismatch, the PA returns to operation under normal conditions.

Note 9: Guaranteed by design and characterization.

MHz

2400

2500

Frequency Range

8

12

15.3

19

24

dBm

3

Output Power

dBm

04

Input Power Range

≥ 2V,

17.3

19