74LVC_LVCH16373A

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Product data sheet

Rev. 8 — 6 January 2014

8 of 17

NXP Semiconductors

74LVC16373A; 74LVCH16373A

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.

Symbol Parameter

Conditions

Min

Typ[1]

Max

Min

Max

propagation

delay

Dn to Qn; see Figure 6

[2]

-

12

-

-

-

ns

1.5

5.4

11.4

1.5

13.2

ns

1.0

2.9

5.7

1.0

6.6

ns

1.5

2.9

4.9

1.5

6.5

ns

1.0

2.4

4.4

1.0

5.5

ns

LE to Qn; see Figure 7

-

14

-

-

-

ns

2.0

6.4

12.4

2.0

14.4

ns

1.5

3.4

6.1

1.5

7.1

ns

1.5

3.0

5.3

1.5

7.0

ns

1.5

2.9

4.8

1.5

6.0

ns

enable time

OE to Qn; see Figure 8

[2]

-

18

-

-

-

ns

1.5

5.5

12.4

1.5

14.3

ns

1.0

3.1

6.6

1.0

7.6

ns

1.5

3.3

5.7

1.5

7.5

ns

1.0

2.5

4.9

1.0

6.5

ns

disable time

OE to Qn; see Figure 8

[2]

-

11

-

-

-

ns

2.8

4.5

9.1

2.8

10.5

ns

1.0

2.5

5.1

1.0

6.0

ns

1.5

3.3

6.3

1.5

8.0

ns

1.5

3.1

5.4

1.5

7.0

ns

pulse width

LE HIGH; see Figure 7

5.0

-

-

5.0

-

ns

4.0

-

-

4.0

-

ns

3.0

-

-

3.0

-

ns

3.0

2.0

-

3.0

-

ns

set-up time

Dn to LE; see Figure 9

3.0

-

-

3.0

-

ns

2.5

-

-

2.5

-

ns

2.0

-

-

2.0

-

ns

2.0

1.0

-

2.0

-

ns