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MAX3804 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX3804 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 9 page 12.5Gbps Settable Receive Equalizer _______________________________________________________________________________________ 5 Pin Description PIN NAME FUNCTION 1, 4 VCC1 CML Input Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Input can also be AC-coupled. 2 SDI+ Positive Serial Data Input, CML 3 SDI- Negative Serial Data Input, CML 5 EQ1 Equalizer Boost Control Logic Input LSB, LVTTL. See Table 1. 6 EQ2 Equalizer Boost Control Logic Input, LVTTL. See Table 1. 7 EQ3 Equalizer Boost Control Logic Input MSB, LVTTL. See Table 1. 8, 16 GND Supply Ground 9, 12 VCC2 CML Output Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Output can also be AC-coupled. 10 SDO- Negative Serial Data Output, CML 11 SDO+ Positive Serial Data Output, CML 13, 14 N.C. No Connection. Leave unconnected. 15 VCC +3.3V Core Supply Voltage EP Exposed Pad Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance (see the Package and Layout Considerations section). Detailed Description General Theory of Operation The MAX3804’s low-noise linear input stage includes two amplifiers, one with flat-frequency response, and one with response that compensates for the loss characteristic of an FR-4 PC board transmission line. A current-steering network allows the designer to control the amount of equalization to match the path loss for specific applications. This network consists of a pair of variable attenuators feeding into a summing node. Equalization is set by a 3-bit LVTTL-compatible input (EQ3, EQ2, and EQ1). By employing fixed control of the equalization level, the MAX3804 provides optimal performance for a specific path loss. A high-speed limiting amplifier follows the equalizer circuitry to shape the output signal (see Figure 1). CML Input and Output Buffers The MAX3804 input and output CML buffers are termi- nated with 50 Ω to VCC1 and VCC2, respectively. The equivalent circuit for the output is shown in Figure 2. Separate supply voltage connections are provided for the core (VCC), input (VCC1), and output (VCC2) circuit- ry to control noise coupling, and to allow DC-coupling to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs and outputs can also be AC-coupled. Use AC-coupling for single-ended cable applications. The unused CML input must be connected through an AC-coupling capacitor to a 50 Ω termination. The low-frequency cutoff of the input-stage offset-can- cellation circuit is nominally 21kHz. |
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