+3.3V, 2.5Gbps, SDH/SONET, 4-Channel

Interconnect Mux/Demux ICs with Clock Generator

6

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7

Self-Test Enable. When this TTL input is forced low, the built-in pattern generator generates

random bits. This also enables an internal serial-system-loopback path. The CML inputs

(SDI± and the SCLK±) and the LVDS inputs are ignored in this mode. An internal 15k

Ω pull-

up resistor pulls TEST high for normal operation.

TEST

9

8

Positive CML Serial-Data Input, 2.488Gbps

SDI+

Negative CML Serial-Data Input, 2.488Gbps

SDI-

12

11

Positive CML Serial-Clock Input, 2.488GHz

SCLKI+

Negative CML Serial-Clock Input, 2.488GHz

SCLKI-

15

14

Negative LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832)

PCLKO-

Positive LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832)

PCLKO+

30

18–23, 26, 27

No Connection

N.C.

Frame Reset. When this TTL input is forced low, the frame detector and pattern generator

are reset. The LOF output is also asserted low. An internal 15k

Ω pull-up resistor pulls

RSETFR high for normal operation.

RSETFR

33

31

TTL Loss-of-Frame Output. Asserts low in a loss-of-frame condition.

LOF

3-State Enable. When this TTL input is forced low, all TTL and LVDS outputs go into a high-

impedance state. An internal 15k

Ω pull-up resistor pulls TRIEN high for normal operation.

TRIEN

35, 37, 40, 42

34, 36, 39, 41

Negative LVDS Parallel-Data Output, 622Mbps

PDO4- to PDO1-

Positive LVDS Parallel-Data Output, 622Mbps

PDO4+ to PDO1+

45, 47, 51, 53

44, 46, 50, 52

Negative LVDS Parallel-Data Input, 622Mbps

PDI4- to PDI1-

Positive LVDS Parallel-Data Input, 622Mbps

PDI4+ to PDI1+

54

Parallel System Loopback Enable. When this TTL input is forced low, the LVDS parallel

inputs route through the elastic store to the LVDS parallel outputs. This bypasses the high-

speed mux and demux. An internal 15k

Ω pull-up resistor pulls PLBEN high for normal oper-

ation.

PLBEN

PIN

FUNCTION

NAME

6

Line Loopback Enable. When this TTL input is forced low, the CML serial-data inputs (SDI±)

route directly to the CML serial-data outputs (SDO±). No other inputs or outputs are affected.

An internal 15k

Ω pull-up resistor pulls LBEN high for normal operation. See Test Loopbacks.

LBEN

4

Positive CML Serial-Data Output, 2.488Gbps

SDO+

3

Negative CML Serial-Data Output, 2.488Gbps

SDO-

2, 5, 10, 13,

17, 24, 38, 55,

59, 64

+3.3V Supply Voltage

1, 16, 25, 28,

29, 32, 43, 48,

49, 60, 63

Supply Ground

GND

Pin Description

56

Negative LVDS Reference Clock Input, 155.52MHz

RCLKI-

57

Positive LVDS Reference Clock Input, 155.52MHz

RCLKI+