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MAX3876 Datasheet(PDF) 6 Page - Maxim Integrated Products

Part # MAX3876
Description  2.5Gbps, Low-Power, 3.3V Clock Recovery and Data Retiming IC
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX3876 Datasheet(HTML) 6 Page - Maxim Integrated Products

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Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadra-
ture VCO outputs on the rising edge of the data input
signal. Depending on the polarity of the frequency dif-
ference, the FD drives the VCO until the frequency dif-
ference is reduced to zero. Once frequency acquisition
is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, CF,
is required to set the PLL damping ratio. See Design
Procedure for guidelines on selecting this capacitor.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low-phase noise
and is trimmed to the correct frequency. Clock jitter
generation is typically 1.5psRMS within a jitter band-
width of 12kHz to 20MHz.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is incorporated in the
MAX3876 frequency detector. A loss-of-lock condition
is signaled immediately with a TTL low. When the PLL is
frequency locked, LOL switches to TTL high in approxi-
mately 800ns.
Note: The LOL monitor is valid only when a data stream
is present on the inputs to the MAX3876. As a result,
LOL does not detect a loss-of-power condition due to
loss of the incoming signal.
Design Procedure
Setting the Loop Filter
The MAX3876 is designed for both regenerator and
receiver applications. Its fully integrated PLL is a clas-
sic second-order feedback system, with a loop band-
width (fL) fixed at 1.5MHz. The external capacitor, CF,
can be adjusted to set the loop damping. Figures 4 and
5 show the open-loop and closed-loop transfer func-
tions.
The PLL zero frequency, fZ, is a function of external
capacitor CF, and can be approximated according to:
For an overdamped system (fZ/fL) < 0.25, the jitter peak-
ing (MP) of a second-order system can be approxi-
mated by:
For example, using CF = 0.1µF results in a jitter peaking
of 0.2dB. Reducing CF below 0.01µF may result in PLL
instability. The recommended value for CF is 1.0µF to
guarantee a maximum jitter peaking of less than 0.1dB.
CF must be a low TC, high-quality capacitor of type
X7R or better.
M
f
f
P
Z
L
=
20log 1+
f
60 C
z
F
=
()
1
2
π
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
6
_______________________________________________________________________________________
CF = 1.0
µF
fZ = 2.6kHz
CF = 0.1
µF
fZ = 26kHz
HO(j2
πf) (dB)
1000
f (kHz)
100
10
1
Figure 4. Open-Loop Transfer Function
CF = 1.0
µF
H(j2
πf) (dB)
1000
100
10
1
f (kHz)
-3
0
CF = 0.1
µF
Figure 5. Closed-Loop Transfer Function


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