Detailed Description

The MAX3935 EAM driver consists of a high-speed

modulation driver and an EAM-biasing block (see

Figure 3). The clock and data inputs to the modulation

driver interface with ECL and CML logic levels. The

-5.2V.

The modulation output stage is composed of a high-

speed differential pair and a programmable current

source rise times a maximum modulation current of

100mA. The rise and fall times are typically 34ps. The

modulation current is designed to produce an EAM

Ω module. The

3.0Vp-p results from 100mA through 50

Ω in parallel

with an internal 75

Ω resistor (30Ω).

Any loading of the EAM module with capacitance

degrades the optical output performance. Because the

BIAS output is connected to the EAM, minimize the par-

asitic capacitance associated with this pad by using an

inductor (L) to isolate the BIAS pin from the EAM.

Clock/Data Input Logic Levels

The MAX3935 is directly compatible with 0V reference

CML. Other logic interfaces are possible with AC-cou-

pling capacitors. For 0V CML of AC-coupled logic, set

10.7Gbps EAM Driver

_______________________________________________________________________________________

7

50

Ω

VOUT

50

Ω

15

Ω

OSCILLOSCOPE

GND

DATA+

DATA-

CLK+

CLK-

-5.2V

50

Ω

50

Ω

50

Ω

50

Ω

DATA+

DATA-

CLK+

CLK-

PATTERN

GENERATOR

-5.2V

MODN1

BIAS

MOD

MODN2

-5.2V

MAX3935EGJ

MODEN

RTEN

Figure 1. AC Characterization Circuit

Pin Description (continued)

PIN

NAME

FUNCTION

26

BIASSET

Bias Current Set. Connected to the output of an external op amp (see the Design Procedure

section).

27

BIASMON

31

MODEN

TTL/CMOS Modulation Enable Input. Low for normal operation, high to put the EAM in the

absorption (logic 0) state. Internal 100k

Ω pullup to GND.

32

RTEN

TTL/CMOS Data Retiming Input. Low for retimed data, high to bypass retiming latch. Internal

100k

Ω pullup to GND.