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BQ24296 Datasheet(PDF) 10 Page - Texas Instruments |
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BQ24296 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 55 page bq24296, bq24297 SLUSBP6B – SEPTEMBER 2013 – REVISED NOVEMBER 2014 www.ti.com Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Hot temperature threshold 2, TS pin As percentage to VREGN REG06[3:2] = 10 VBHOT2 29.5% 30% 30.5% voltage falling threshold (Approx. 65°C w/ 103AT) As percentage to VREGN REG06[3:2] = 10 VBHOT2_HYS 3% (Approx. 3°C w/ 103AT) CHARGE OVER-CURRENT COMPARATOR HSFET cycle by cycle over-current IHSFET_OCP 5.3 7.5 A threshold IBATFET_OCP System over load threshold 5.5 6.6 A LSFET charge under-current falling VLSFET_UCP From sync mode to non-sync mode 100 mA threshold PWM Switching frequency, and digital FSW 1300 1500 1700 kHz clock DMAX Maximum PWM duty cycle 97% VBTST-VSW when LSFET refresh pulse is requested, VBTST_REFRESH Bootstrap refresh comparator threshold 3.6 V VBUS = 5 V BOOST MODE OPERATION VOTG_REG_ACC OTG output voltage I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) 5 V VOTG_REG_ACC OTG output voltage accuracy I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) -3% 3% VOTG_BAT Battery voltage exiting OTG mode BAT falling, REG04[1] = 1 2.9 V REG01[0] = 0 1 A IOTG OTG mode output current REG01[0] = 1 1.5 A VOTG_OVP OTG over-voltage threshold Rising threshold 5.8 6 V VOTG_OVP_HYS OTG over-voltage threshold hysteresis Falling threshold 300 mV IOTG_LSOCP LSFET cycle by cycle current limit 5 A IOTG_HSZCP HSFET under current falling threshold 100 mA REG01[0] = 0 1.00 1.15 1.30 IRBFET_OCP RBFET over-current threshold A REG01[0] = 1 1.50 1.70 1.90 REGN LDO VVBUS = 6 V, IREGN = 40 mA 4.8 5 5.5 V VREGN REGN LDO output voltage VVBUS = 5 V, IREGN = 20 mA 4.7 4.8 V IREGN REGN LDO current limit VVBUS = 5 V, VREGN = 3.8 V 50 mA LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG) VILO Input low threshold 0.4 V Input high threshold (CE, STAT, QON, VIH 1.3 V PSEL, PG) VIH_OTG Input high threshold (OTG) 1.1 V VOUT_LO Output low saturation voltage Sink current = 5 mA 0.4 V High level leakage current (OTG, CE, IBIAS Pull-up rail 1.8 V 1 µA STAT , PSEL, PG) IBIAS High level leakage current (QON) Pull-up rail 3.6 V 8 µA I2C INTERFACE (SDA, SCL, INT) VIH Input high threshold level VPULL-UP = 1.8 V, SDA and SCL 1.3 V VIL Input low threshold level VPULL-UP = 1.8 V, SDA and SCL 0.4 V VOL Output low threshold level Sink current = 5 mA 0.4 V IBIAS High-level leakage current VPULL-UP = 1.8 V, SDA and SCL 1 µA fSCL SCL clock frequency 400 kHz DIGITAL CLOCK AND WATCHDOG TIMER fHIZ Digital crude clock REGN LDO disabled 15 35 50 kHz fDIG Digital clock REGN LDO enabled 1300 1500 1700 kHz 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 |
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