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74LVT241 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVT241 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 74LVT241_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 May 2008 3 of 16 NXP Semiconductors 74LVT241 3.3 V octal buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20 74LVT241 1OE VCC 1A0 2OE 2Y0 1Y0 1A1 2A0 2Y1 1Y1 1A2 2A1 2Y2 1Y2 1A3 2A2 2Y3 1Y3 GND 2A3 001aah734 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aah735 74LVT241 GND(1) Transparent top view 1Y3 1A3 2Y3 2A2 2Y2 1Y2 1A2 2A1 2Y1 1Y1 1A1 2A0 2Y0 1Y0 1A0 2OE 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area Table 2. Pin description Symbol Pin Description 1OE 1 output enable input (active LOW) 1A0 to 1A3 2, 4, 6, 8 data input 2A0 to 2A3 17, 15, 13, 11 data input GND 10 ground (0 V) 1Y0 to 1Y3 18, 16, 14, 12 data output 2Y0 to 2Y3 3, 5, 7, 9 data output 2OE 19 output enable input (active HIGH) VCC 20 supply voltage |
Similar Part No. - 74LVT241_15 |
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Similar Description - 74LVT241_15 |
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