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74FCT38075S Datasheet(PDF) 2 Page - Integrated Device Technology

Part # 74FCT38075S
Description  Extremely low RMS Additive Phase Jitter
Download  11 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

74FCT38075S Datasheet(HTML) 2 Page - Integrated Device Technology

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LOW SKEW 1 TO 5 CLOCK BUFFER
2
REVISION A 03/18/15
74FCT38075S DATASHEET
Pin Assignments
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be
connected between VDD on pin 2 and GND on pin 4, as close to the device as possible. A 33
 series terminating resistor may
be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 74FCT38075S is capable of, careful attention must be paid to board layout. Essentially,
all five outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew
will be degraded. For example, using a 30
 series termination on one output (with 33 on the others) will cause at least 15 ps
of skew.
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
Q4
Output
Clock Output 4.
2
VDD
Power
Connect to +1.8V, +2.5 V, or +3.3 V.
3
ICLK
Input
Clock input.
4
GND
Power
Connect to ground.
5
Q0
Output
Clock output 0.
6
Q1
Output
Clock output 1.
7
Q2
Output
Clock Output 2.
8
Q3
Output
Clock Output 3.
1
2
3
ICLK
4
Q0
Q1
Q3
Q4
Q2
VDD
8
7
6
5
GND
8-pin SOIC
1
2
3
ICLK
4
Q0
Q1
Q3
Q4
Q2
VDD
8
7
6
5
GND
8-pin DFN


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