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8705I Datasheet(PDF) 3 Page - Integrated Device Technology

Part # 8705I
Description  Output frequency range
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

8705I Datasheet(HTML) 3 Page - Integrated Device Technology

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REVISION E 7/13/15
8705I DATA SHEET
3
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
TABLE 3A. PLL ENABLE FUNCTION TABLE
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q0:Q7
0
000
÷ 8
0
001
÷ 8
0
010
÷ 8
0
0
1
1
÷ 16
0
1
0
0
÷ 16
0
1
0
1
÷ 16
0
1
1
0
÷ 32
0
1
1
1
÷ 32
1
0
0
0
÷ 64
1
0
0
1
÷ 128
1
010
÷ 4
1
011
÷ 4
1
100
÷ 8
1
101
÷ 2
1
110
÷ 4
1
111
÷ 2
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)
Q0:Q7
0
0
0
0
125 - 250
÷ 1
0
0
0
1
62.5 - 125
÷ 1
0
0
1
0
31.25 - 62.5
÷ 1
0
0
1
1
15.625 -31.25
÷ 1
0
1
0
0
125 - 250
÷ 2
0
1
0
1
62.5 - 125
÷ 2
0
1
1
0
31.25 - 62.5
÷ 2
0
1
1
1
125 - 250
÷ 4
1
0
0
0
62.5 - 125
÷ 4
1
0
0
1
125 - 250
÷ 8
1
0
1
0
62.5 - 125
x 2
1
0
1
1
31.25 - 62.5
x 2
1
1
0
0
15.625 - 31.25
x 2
1
1
0
1
31.25 - 62.5
x 4
1
1
1
0
15.625 - 31.25
x 4
1
1
1
1
15.625 - 31.25
x 8


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