8705I datasheet(5/18 Pages) IDT | Output frequency range

Part #	8705I

Description	Output frequency range

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Manufacturer	IDT [Integrated Device Technology]

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REVISION E 7/13/15

8705I DATA SHEET

5

Zero Delay, Differential-to-LVCMOS/

LVTTL Clock Generator

TABLE 5A. AC CHARACTERISTICS, V

DD = VDDA = VDDO = 3.3V±5%, TA = -40°C

TO

85°C

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V

DD = VDDA = VDDO = 3.3V±5%, TA = -40°C

TO

85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Output Frequency

15.625

250

MHz

tp

LH

Propagation Delay,

Low-to-High; NOTE 1

CLK0

PLL_SEL = 0V,

f

≤ 250MHz, Qx ÷ 2

57

ns

CLK1, nCLK1

PLL_SEL = 0V,

f

≤ 250MHz, Qx ÷ 2

5

7.3

ns

t(Ø)

Static Phase Offset;

NOTE 2, 4

CLK0

PLL_SEL = 3.3V,

fREF

≤ 200MHz, Qx ÷ 1

-100

25

150

ps

CLK1, nCLK1

PLL_SEL = 3.3V,

fREF

≤ 167MHz, Qx ÷ 1

-15

+135

285

ps

PLL_SEL = 3.3V,

fREF = 200MHz, Qx ÷ 1

-50

+100

250

ps

tsk(o)

Output Skew;

NOTE 3, 4

CLK0

PLL_SEL = 0V

65

ps

CLK1, nCLK1

PLL_SEL = 0V

55

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 4

f

OUT > 40MHz

45

ps

t

L

PLL Lock Time

1mS

t

R

Output Rise Time

400

950

ps

t

F

Output Fall Time

400

950

ps

odc

Output Duty Cycle

43

57

%

All parameters measured at f

MAX unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at V

DDO/2.

NOTE 2: Deﬁned as the time difference between the input reference clock and the average feedback input signal

when the PLL is locked and the input reference frequency is stable.

NOTE 3: Deﬁned as skew between outputs at the same supply voltages and with equal load conditions.

Measured at V

DDO/2.

NOTE 4: This parameter is deﬁned in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

I

IH

Input High Current

CLK1

V

DD = VIN = 3.465V

150

µA

nCLK1

V

DD = VIN = 3.465V

5

µA

I

IL

Input Low Current

CLK1

V

DD = 3.465V, VIN = 0V

-5

µA

nCLK1

V

DD = 3.465V, VIN = 0V

-150

µA

V

PP

Peak-to-Peak Input Voltage

0.15

1.3

V

CMR

Common Mode Input Voltage;

NOTE 1, 2

GND + 0.5

V

DD - 0.85

V

NOTE 1: Common mode voltage is deﬁned as V

IH.

NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is V

DD + 0.3V.

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