87002-02 datasheet(7/16 Pages) IDT | Output frequency range

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87002-02 Datasheet(PDF) 7 Page - Integrated Device Technology

Part #	87002-02

Description	Output frequency range

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK

GENERATOR

Rev C 7/13/15

87002-02 DATA SHEET

AC Electrical Characteristics

Table 5A. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.

NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and

the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Table 5B. AC Characteristics, VDD = VDDA = VDDO = 2.5V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.

NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and

the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

15.625

250

MHz

tPD

Propagation Delay; NOTE 1

PLL_SEL = 0V, f

 250MHz,

Qx ÷ 2

4.8

5.8

t(Ø)

Static Phase Offset; NOTE 2, 4

PLL_SEL = 3.3V,

fREF  167MHz, Qx ÷ 1

-160

-10

140

tsk(o)

Output Skew; NOTE 3, 4

PLL_SEL = 0V

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 4

fOUT > 40MHz

PLL Lock Time

1ms

tR / tF

Output Rise/Fall Time

20% to 80%

400

800

odc

Output Duty Cycle