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ICS670-02 Datasheet(PDF) 2 Page - Integrated Device Technology |
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ICS670-02 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 7 page ICS670-02 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 2 ICS670-02 REV J 051310 Pin Assignment Multiplier Select Table Pin Descriptions 12 1 11 2 10 3 9 VDD 4 VDD 5 VDD 6 GND 7 CLK2 8 OE2 GND S0 S1 FBCLK S3 OE1 ICLK 16 15 14 13 FBIN GND S2 S3 S2 S1 S0 CLK2 (and FBCLK) Input Range (MHz) 0000 Low (Power down entire chip) - 0001 Input x1.333 18 - 120 0010 Input x6 5 - 26.67 0011 Input x1.5 16.67 - 107 0100 Input x3.333 7.5 - 48 0101 Input x2.50 10 - 64 0110 Input x4 6 - 40 0111 Input x1 25 - 160 1000 Input x2.333 11 - 69 1001 Input x2.666 10 - 60 1010 Input x12 5 - 13.33 1011 Input x3 8 - 53.33 1100 Input x10 5 - 16 1101 Input x5 6 - 32 1110 Input x8 5 - 20 1111 Input x2 12 - 80 Pin Number Pin Name Pin Type Pin Description 1 - 3 VDD Input Power supply. Connect both pins to the same voltage (either 3.3 V or 5 V). 4 CLK2 Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 5 OE2 Input Output clock enable 2. Tri-states the clock 2 output when low. 6 FBCLK Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 7 OE1 Input Output clock enable 1. Tri-states the feedback clock output when low. 8 FBIN Input Feedback clock input. 9 ICLK Input Clock input. Connect to a 5 - 160 MHz clock. 10 S3 Input Multiplier select pin 3. Determines outputs per table above. Internal pull-up. 11 S2 Input Multiplier select pin 2. Determines outputs per table above. Internal pull-up. 12 S1 Input Multiplier select pin 1. Determines outputs per table above. Internal pull-up. 13 S0 Input Multiplier select pin 0. Determines outputs per table above. Internal pull-up. 14 - 16 GND Power Connect to ground. |
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