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ICS853S012I Datasheet(PDF) 11 Page - Integrated Device Technology |
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ICS853S012I Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 22 page  ICS853S012I Data Sheet 12-:1, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL CLOCK/DATA MULTIPLEXER ICS853S0121AKI REVISION A SEPTEMBER 28, 2012 11 ©2012 Integrated Device Technology, Inc. 3.3V Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, CML and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the IN/nIN input with built-in 50 terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. Figure 2A. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2C. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2E. CLK/nCLK Input Driven by an IDT Open Collector CML Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. CLK/nCLK Input Driven by a Built-In Pullup CML Driver R3 125 Ω R4 125 Ω R1 84 Ω R2 84 Ω 3.3V Zo = 50 Ω Zo = 50 Ω CLK nCLK 3.3V 3.3V LVPECL Differential Input 3.3V R1 100 Ω LVDS CLK nCLK 3.3V Receiver Zo = 50 Ω Zo = 50 Ω CLK nCLK Differential Input CML 3.3V Zo = 50 Ω Zo = 50 Ω 3.3V 3.3V R1 50 R2 50 CLK nCLK Differential Input LVPECL 3.3V Zo = 50 Ω Zo = 50 Ω 3.3V R1 50 Ω R2 50 Ω R2 50 Ω 3.3V R1 100 CML Built-In Pullup CLK nCLK 3.3V Differential Input Zo = 50 Ω Zo = 50 Ω |
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