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ICS853S057I Datasheet(PDF) 9 Page - Integrated Device Technology |
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ICS853S057I Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 16 page ICS853S057I Data Sheet 4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER ICS853S057AGI REVISION A MAY 16, 2012 9 ©2012 Integrated Device Technology, Inc. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 3.3V V CC - 2V R1 50 Ω R2 50 Ω RTT Z o = 50Ω Z o = 50Ω + _ RTT = * Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input R1 84 Ω R2 84 Ω 3.3V R3 125 Ω R4 125 Ω Z o = 50Ω Z o = 50Ω LVPECL Input 3.3V 3.3V + _ |
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