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BLF8G20LS-260A Datasheet(PDF) 5 Page - NXP Semiconductors |
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BLF8G20LS-260A Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 15 page BLF8G20LS-260A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 12 July 2013 5 of 15 NXP Semiconductors BLF8G20LS-260A Power LDMOS transistor [1] ZS and ZL defined in Figure 1. [2] at 3 dB gain compression. 7.3 Recommended impedances for Doherty design [1] ZS and ZL defined in Figure 1. [2] at 3 dB gain compression. [3] at PL(AV) = 47 dBm. [1] ZS and ZL defined in Figure 1. [2] at 3 dB gain compression. [3] at PL(AV) = 47 dBm. Maximum drain efficiency load 1810 0.8 j3.7 2.6 j2.6 176 67 18.1 1840 0.7 j3.9 2.4 j2.4 162 66 18.3 1880 0.7 j4.0 2.3 j2.5 163 65 18.4 Fig 1. Definition of transistor impedance Table 10. Typical impedance of peak device …continued Measured load-pull data of peak device; IDq = 1200 mA (peak); VDS = 28 V. f ZS[1] ZL[1] PL[2] D [2] Gp[2] (MHz) ( ) ( ) (W) (%) (dB) 001aaf059 drain ZL ZS gate Table 11. Typical impedance of main device at 1 : 1 load Measured load-pull data of main device; IDq = 750 mA (main); VDS = 28 V. f ZS[1] ZL[1] PL[2] D [3] Gp[3] (MHz) ( ) ( ) (dBm) (%) (dB) 1810 1.0 j3.7 1.4 j4.1 52.38 33.8 18.0 1840 1.0 j3.9 1.4 j3.8 52.23 34.3 18.1 1880 1.1 j4.0 1.3 j3.6 52.08 35.0 18.3 Table 12. Typical impedance of main device at 1 : 2.5 load Measured load-pull data of main device; IDq = 750 mA (main); VDS = 28 V. f ZS[1] ZL[1] PL[2] D [3] Gp[3] (MHz) ( ) ( ) (dBm) (%) (dB) 1810 1.0 j3.7 2.4 j2.6 50.83 47.3 20.2 1840 1.0 j3.9 2.8 j3.0 50.47 50.2 20.8 1880 1.1 j4.0 3.1 j2.7 50.25 50.9 21.2 |
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