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BLF8G24LS-150V Datasheet(PDF) 2 Page - NXP Semiconductors |
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BLF8G24LS-150V Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 16 page BLF8G24LS-150V_8G24LS-150GV All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 12 May 2014 2 of 16 NXP Semiconductors BLF8G24LS-150(G)V Power LDMOS transistor 2. Pinning information [1] Connected to flange. 3. Ordering information 4. Limiting values [1] Continuous use at maximum temperature will affect the reliability, for details refer to the on-line MTF calculator. Table 2. Pinning Pin Description Simplified outline Graphic symbol BLF8G24LS-150V (SOT1244B) 1drain 2gate 3source [1] 4 decoupling lead 5 decoupling lead 6n.c. 7n.c. BLF8G24LS-150GV (SOT1244C) 1drain 2gate 3source [1] 4 decoupling lead 5 decoupling lead 6n.c. 7n.c. Table 3. Ordering information Type number Package Name Description Version BLF8G24LS-150V - earless flanged ceramic package; 6 leads SOT1244B BLF8G24LS-150GV - earless flanged ceramic package; 6 leads SOT1244C Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage - 65 V VGS gate-source voltage 0.5 +13 V Tstg storage temperature 65 +150 C Tj junction temperature [1] - 225 C |
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