BLF7G15LS-300P

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Product data sheet

Rev. 3 — 12 July 2013

4 of 11

NXP Semiconductors

BLF7G15LS-300P

Power LDMOS transistor

7.2 Impedance information

7.3 Graphs

Table 9.

Typical impedance per section (for the maximum peak power)

f

(MHz)

(

)

(

)

1410

0.65

 j2.06

6.3

 j2.1

1480

0.55

 j1.92

7.2

 j1.3

1560

0.63

 j2.14

6.8 + j0.26

Fig 1.

Definition of transistor impedance

001aaf059

drain

gate

(1) f = 1476 MHz

(2) f = 1511 MHz

Fig 2.

One-tone CW power gain and drain efficiency as function of load power;

typical values

0

100

200

300

350

250

150

50

001aam553

14

18

22

12

16

20

(dB)

10

20

40

60

10

30

50

(%)

0

(1)

(2)