UVLO

Thermal

Shutdown

Current

Limit

Enable

Error

Amp

IN

EN

OUT

FB

Pass

Device

Power

Good

Control

DELAY

PG

TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1

www.ti.com

SBVS188C – MARCH 2012 – REVISED DECEMBER 2014

7 Detailed Description

7.1 Overview

The TPS7A16xx-Q1 family of devices is ultra low power, low-dropout (LDO) voltage regulators that offers the

benefits of ultra-low quiescent current, high input voltage, and miniaturized, high thermal-performance packaging.

TPS7A16xx-Q1 family also offers an enable pin (EN) and integrated open-drain active-high power-good output

(PG) with a user-programmable delay.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Enable (EN)

The enable terminal is a high-voltage-tolerant terminal. A high input on EN actives the device and turns on the

initial power up, the regulator has a soft start incorporated to control the initial current through the pass element.

In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load

current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage

recovers above the minimum start-up level.

7.3.3 PG Delay Timer (DELAY)

connected from the DELAY pin to GND; this capacitor is charged from 0 V to ~1.8 V by the DELAY pin current

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Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1