ICS854S057BI Data Sheet

4:1, OR 2:1 LVDS CLOCK MULTIPLEXER W/INTERNAL INPUT TERMINATION

ICS854S057BGI REVISION A MARCH 29, 2010

9

©2010 Integrated Device Technology, Inc.

The PCLK /nPCLK with built-in 50

Ω terminations accept LVDS,

LVPECL, CML, SSTL and other differential signals. Both differential

to 2E show interface examples for the PCLK /nPCLK with built-in 50

Ω

termination input driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from

another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

Figure 2A. PCLK/nPCLK Input with

Built-In 50

Ω Driven by an LVDS Driver

Figure 2C. PCLK/nPCLK Input with

Built-In 50

Ω Driven by a CML Driver

Figure 2E. PCLK/nPCLK Input with

Built-In 50

Ω Driven by an SSTL Driver

Figure 2B. PCLK/nPCLK Input with

Built-In 50

Ω Driven by an LVPECL Driver

Figure 2D. PCLK/nPCLK Input with Built-In 50

Ω Driven

by a CML Driver with Built-In 50

Ω Pullup

PCLK

nPCLK

VT

Receiver

With

Built-In

50

Ω

LVDS

3.3V or 2.5V

2.5V

Zo = 50

Ω

Zo = 50

Ω

PCLK

nPCLK

VT

CML

Receiver

With

Built-In

50

Ω

2.5V

2.5V

Zo = 50

Ω

Zo = 50

Ω

SSTL

R1

25

Ω

R2

25

Ω

PCLK

nPCLK

VT

Receiver

With

Built-In

50

Ω

2.5V

2.5V

Zo = 50

Ω

Zo = 50

Ω

PCLK

nPCLK

VT

Receiver

With

Built-In

50

Ω

R1

18

Ω

LVPECL

2.5V

2.5V

Zo = 50

Ω

Zo = 50

Ω

CML - Built-in 50

Ω Pull-up

PCLK

nPCLK

VT

Receiver

With

Built-In

50

Ω

2.5V

2.5V

Zo = 50

Ω

Zo = 50

Ω