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ICS8745BI-21 Datasheet(PDF) 7 Page - Integrated Device Technology |
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ICS8745BI-21 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 21 page  ICS8745BMI-21 REVISION D JULY 28, 2010 7 ©2010 Integrated Device Technology, Inc. ICS8745BI-21 Data Sheet 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR AC Electrical Characteristics Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 700 MHz tPD Propagation Delay; NOTE 1 PLL_SEL = 0V, f ≤ 700MHz 2.9 3.4 4.0 ns tsk(Ø) Static Phase Offset; NOTE 2, 5 PLL_SEL = 3.3V -100 25 150 ps tsk(o) Output Skew; NOTE 3, 5 40 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 5, 6 30 ps tjit( θ) Phase Jitter; NOTE 4, 5, 6 ±52 ps tL PLL Lock Time 1ms tR / tF Output Rise/Fall Time; NOTE 7 20% to 80% 200 700 ps odc Output Duty Cycle 45 50 55 % |
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