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ICS8745BI-21 Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS8745BI-21 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 21 page  ICS8745BMI-21 REVISION D JULY 28, 2010 10 ©2010 Integrated Device Technology, Inc. ICS8745BI-21 Data Sheet 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Applications Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8745BI-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels VDD VDDA 3.3V 10 Ω 10µF .01µF .01µF |
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