completion of the startup delay period, and no watch-

dog output pulses are asserted during the startup

delay. When the startup delay expires, the watchdog

begins counting its normal watchdog timeout period

and waiting for WDI transitions. The startup delay

allows time for the µP system to power up and fully ini-

tialize before assuming responsibility for the normal

watchdog timer updates. Startup delay periods vary

between the different devices and may be altered by

the logic control set pins. To ensure that the system

generates no undesired watchdog outputs, the routine

watchdog input transitions should begin before the

selected minimum startup delay period has expired.

The normal watchdog timeout period countdown is initi-

ated when the startup delay is complete. If a valid logic

transition is not recognized at WDI before the watchdog

timeout period has expired, the supervisor asserts a

watchdog output. Watchdog timeout periods vary

between the different devices and may be altered by

the logic control set pins. To ensure that the system

generates no undesired watchdog outputs, the watch-

dog input transitions should occur before the selected

minimum watchdog timeout period has expired.

The startup delay and the watchdog timeout period are

determined by the states of the SET0, SET1, and SET2

pins, and by the particular device within the family. For

the MAX6369 and MAX6370, the startup delay is equal

to the watchdog timeout period. The startup and

watchdog timeout periods are pin selectable from 1ms

to 60s (minimum).

For the MAX6371 and MAX6372, the startup delay is

fixed at 60s and the watchdog timeout period is pin

selectable from 1ms to 60s (minimum).

The MAX6373/MAX6374 provide two timing variations

for the startup delay and normal watchdog timeout.

Five of the pin-selectable modes provide startup delays

from 200µs to 60s minimum, and watchdog timeout

delays from 3ms to 10s minimum. Two of the selectable

modes do not initiate the watchdog timer until the

device receives its first valid watchdog input transition

(there is no fixed period by which the first input must be

received). These two extended startup delay modes

are useful for applications requiring more than 60s for

system initialization.

All the MAX6369–MAX6374 devices may be disabled

with the proper logic control pin setting (Table 1).

Applications Information

Input Signal Considerations

Watchdog timing is measured from the last WDI rising

or falling edge associated with a pulse of at least 100ns

in width. WDI transitions are ignored when WDO is

asserted, and during the startup delay period (Figure

2). Watchdog input transitions are also ignored for a

a setting change (Figure 3).

Selecting Device Timing

SET2, SET1, and SET0 program the startup delay and

watchdog timeout periods (Table 1). Timeout settings

can be hard wired, or they can be controlled with logic

gates and modified during operation. To ensure smooth

transitions, the system should strobe WDI immediately

before the timing settings are changed. This minimizes

the risk of initializing a setting change too late in the

timer countdown period and generating undesired

watchdog outputs. After changing the timing settings,

two outcomes are possible based on WDO. If the

change is made while WDO is asserted, the previous

setting is allowed to finish, the characteristics of the

new setting are assumed, and the new startup phase is

the change is made while WDO is not asserted, the

new setting is initiated immediately, and the new start-

up phase is entered after the 300µs setup time elapses.

Pin-Selectable Watchdog Timers

_______________________________________________________________________________________

7

**

*

*

*

*IGNORED EDGE

WDI

WDO

SET_

Figure 3. Setting Change Timing