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ADS58J63 Datasheet(PDF) 11 Page - Texas Instruments |
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ADS58J63 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 87 page  CLKINM Data Latency: 77 Clock Cycles N TPD CLKINP DAP/M DBP/M DCP/M DDP/M SAMPLE N SAMPLE N+1 SAMPLE N-1 D 20 D 1 D 20 SAMPLE N+1 N+2 ADS58J63 www.ti.com SBAS717A – JUNE 2015 – REVISED JUNE 2015 6.8 Timing Characteristics Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input, unless otherwise noted. MIN TYP MAX UNITS SAMPLE TIMING CHARACTERISTICS Aperture delay 0.75 1.6 ns Aperture delay matching between two channels on the same device ±70 ps Aperture delay matching between two devices at the same temperature and supply voltage ±270 ps Aperture jitter 135 fS rms Wake-up time to valid data after coming out of global power-down 150 µs Input Data Latency(1) ADC sample to digital output 77 Clock Cycles Input OVR Latency ADC sample to OVR bit 44 Clock Cycles Input clock rising edge cross-over to output clock rising edge tPDI Clock propagation delay 4 ns cross-over tSU_SYSREF Setup time for SYSREF, referenced to input clock rising edge 300 900 ps tH_SYSREF Hold time for SYSREF, referenced to input clock rising edge 100 ps JESD OUTPUT INTERFACE TIMING CHARACTERISTICS Unit interval 100 400 ps Serial output data rate 2.5 10 Gbps Total jitter for BER of 1E-15 and lane rate = 10 Gbps 26 ps Random jitter for BER of 1E-15 and lane rate = 10 Gbps 0.75 ps rms Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 12 ps, pk-pk Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output tR, tF 35 ps waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps (1) Overall ADC Latency = Data Latency + tPDI Figure 1. Latency Timing Diagram Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADS58J63 |
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