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IRUH330133A Datasheet(PDF) 5 Page - International Rectifier |
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IRUH330133A Datasheet(HTML) 5 Page - International Rectifier |
5 / 9 page www.irf.com 5 IRUH330133AK IRUH330133AP Input Capacitance Input bypass capacitors: Two (0.1 µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX TPS or equivalent), placed very close to the V IN Pin are required for proper operation. When the input voltage supply capacitance is more than 4 inches from the device, additional input capacitance is recommended. Larger input capacitor values will improve ripple rejection further improving the integrity of the output voltage. Output Capacitance Output bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX TPS or equivalent) are required for loop stability. Faster transient performance can be achieved with multiple additional 1µF ceramic capacitors. Ceramic capacitors greater than 1µF in value are not recommended as they can cause stability issues. Tantalum capacitor values larger than the suggested value are recommended to improve the transient response under large load current changes. The upper capacitance value limit is governed by the delayed over-current latch function of the regulator and can be as much as 10,000µF without causing the device to latch-off during start-up. General Layout Rules Low impedance connections between the regulator output and load are essential. Solid power and ground planes are highly recommended. In those cases where the board impedances are not kept very small, oscillations can occur due to the effect of parasitic series resistance and inductance on loop bandwidth and phase margin. The V SENSE Pin must be connected directly to the VOUT Pin using as short a trace as possible with the connection inside the first bypass capacitor (see Fig. 2a). Connect ceramic output capacitors directly across the V OUT and GND Pins with as wide a trace as design rules allow (see Fig. 2a). Avoid the use of vias for these capacitors and avoid loops. Fig.2 shows the ceramic capacitors tied directly to the regulator output. Fig. 2a. Layer 1 conductor. Ground plane below layer 1 Fig. 2b. Layer 1 silkscreen The input capacitors should be connected as close a possible to the V IN Pin. |
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