16

15

OC_ADJ

14

RESET

13

C_STARTUP

12

INPUT_A

11

INPUT_B

10

VI_CM

9

GND

8

AGND

7

VREG

6

INPUT_C

5

INPUT_D

4

FREQ_ADJ

3

OSC_IO+

2

OSC_IO-

1

SD

64-pins QFP package

33

GND_D

34

GND_C

35

GND_C

36

OUT_C

37

OUT_C

38

PVDD_C

39

PVDD_C

40

BST_C

41

BST_B

42

PVDD_B

43

OUT_B

44

GND_B

45

GND_A

46

47

48

OTW1

PVDD_B

OUT_B

GND_B

PHD PACKAGE

(TOP VIEW)

PIN ONE LOCATION PHD PACKAGE

Pin 1 Marker

White Dot

Electrical Pin 1

TAS5611A

SLAS709B

– JUNE 2010 – REVISED JULY 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DEVICE INFORMATION

Pin Assignment

The TAS5611A is available in a thermally enhanced packages:

•

64-Pin QFP (PHD) Power Package

The package types contain heat slugs that are located on the top side of the device for convenient thermal

coupling to the heat sink.

MODE SELECTION PINS

MODE PINS

OUTPUT

ANALOG INPUT

DESCRIPTION

CONFIGURATION

M3

M2

M1

0

0

0

Differential

2

× BTL

AD mode

0

0

1

—

—

Reserved

0

1

0

Differential

2

× BTL

BD mode

Differential Single

0

1

1

1

× BTL +2 ×SE

BD mode, BTL Differential

Ended

1

0

0

Single Ended

4

× SE

AD mode

1

0

1

Differential

1

× PBTL

0

0

AD mode

1

0

BD mode

1

1

0

Reserved

1

1

1

(1)

INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=GND).

2

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© 2010–2011, Texas Instruments Incorporated