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TAS5760M Datasheet(PDF) 5 Page - Texas Instruments |
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TAS5760M Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 84 page  TAS5760M www.ti.com SLOS772D – JULY 2013 – REVISED JULY 2015 Pin Functions (continued) TAS5760M NO. TYPE(1) INTERNAL TERMINATION DESCRIPTION NAME Connection point for the SPK_OUTA- bootstrap capacitor, which is used to BSTRPA- 39 P - create a power supply for the high-side gate drive for SPK_OUTA- Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to BSTRPA+ 43 P - create a power supply for the high-side gate drive for SPK_OUTA Connection point for the SPK_OUTB- bootstrap capacitor, which is used to BSTRPB- 38 P - create a power supply for the high-side gate drive for SPK_OUTB- Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to BSTRPB+ 34 P - create a power supply for the high-side gate drive for SPK_OUTB+ Ground for digital circuitry (NOTE: This pin should be connected to the DGND 17 G - system ground) DVDD 9 P - Power supply for the internal digital circuitry Dual function pin that functions as an I²C data input pin in I²C Control Mode FREQ/SDA 7 DI Weak Pull-Down or as a Frequency Select terminal when in Hardware Control Mode. Ground for gate drive circuitry (this terminal should be connected to the GGND 47 G - system ground) Voltage regulator derived from PVDD supply (NOTE: This pin is provided as GVDD_REG 48 P - a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) Word select clock for the digital signal that is active on the serial port's input LRCK 16 DI Weak Pull-Down data line Master Clock used for internal clock tree, sub-circuit/state machine, and MCLK 13 DI Weak Pull-Down Serial Audio Port clocking Not connected inside the device (all "no connect" pins should be connected 18- NC - - to ground for best thermal performance, however they can be used as 31 routing channels if required.) Dual function pin that functions as an I²C clock input terminal in I²C Control PBTL/SCL 8 DI Weak Pull-Down Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in Hardware Control Mode 36, Ground for power device circuitry (NOTE: This terminal should be PGND G - 41 connected to the system ground) 32, 33, PVDD P - Power Supply for internal power circuitry 44, 45 Bit clock for the digital signal that is active on the serial data port's input SCLK 14 DI Weak Pull-Down data line SDIN 15 DI Weak Pull-Down Data line to the serial data port SFT_CLIP 1 AI - sets the maximum output voltage before clipping Speaker amplifier fault terminal, which is pulled LOW when an internal fault SPK_FAULT 5 DO - occurs SPK_GAIN0 10 DI Weak Pull-Down Adjusts the LSB of the multi-bit gain of the speaker amplifier SPK_GAIN1 11 DI Weak Pull-Down Adjusts the MSB of the multi-bit gain of the speaker amplifier SPK_SLEEP/ In Hardware Control Mode, places the speaker amplifier in sleep mode. In 12 DI Weak Pull-Up ADR Software Control Mode, is used to determine the I²C Address of the device SPK_OUTA- 40 AO - Negative pin for differential speaker amplifier output A SPK_OUTA+ 42 AO - Positive pin for differential speaker amplifier output A SPK_OUTB- 37 AO - Negative pin for differential speaker amplifier output B SPK_OUTB+ 35 AO - Positive pin for differential speaker amplifier output B SPK_SD 6 AO - Places the speaker amplifier in shutdown VCOM 3 P - Bias voltage for internal PWM conversion block Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the PowerPAD™ - G - device connected to it via solder. For proper electrical operation, this ground pad must be connected to the system ground. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TAS5760M |
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