DAC161S997

SNAS621A – JUNE 2013 – REVISED DECEMBER 2014

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8.5 Programming

8.5.1 Serial Interface

The 4-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs. See the Timing

Requirements section for timing information about the read and write sequences. The serial interface is

comprised of CSB, SCLK, SDIs and SDO. The DAC161S997 supports both Mode 0 and Mode 3 of the SPI

protocol.

A bus transaction is initiated by the falling edge of CSB. When CSB is low, the input data is sampled at the SDI

pin by the rising edge of the SCLK. The output data is asserted on the SDO pin at the falling edge of SCLK.

A valid transfer requires an integer multiple of 24 SCLK cycles. If CSB is raised before the 24th rising edge of the

SCLK, the transfer aborts and a Frame Error is reported. If CSB is held low after the 24th falling edge of the

SCLK and additional SCLK edges occur, the data continues to flow through the FIFO and out the SDO pin.

When CSB transitions high, the internal controller decodes the most recent 24 bits that were received before the

rising edge of CSB. CSB must transition to high after an integer multiple of 24 clock cycles, otherwise a Frame

Error is reported and the transaction is considered invalid. When a valid number of SCLK pulses occur with CSB

low, the DAC then performs the requested operation after CSB transitions high.

Figure 8. SPI Data Format

The acquired data is shifted into an internal 24-bit shift register (MSB first) which is configured as a 24-bit deep

FIFO. As the data is being shifted into the FIFO via the SDI pin, the prior contents of the register are being

shifted out through the SDO output. While CSB is high, SDO is in a high Z-state. At the falling edge of CSB, SDO

presents the MSB of the data present in the shift register. SDO is updated on every subsequent falling edge of

SCLK.

NOTE

The first SDO transition will happen on the first falling edge AFTER the first rising edge of

SCLK when CSB is low.

The 24 bits of data contained in the FIFO are interpreted as an 8-bit COMMAND word followed by 16-bits of

DATA. The general format of the 24-bit data stream is shown in Figure 9. Complete instruction set is tabulated in

the Detailed Description section.

Figure 9. SPI Command and Data Words

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