ISL6269A

10

FN9253.3

November 18, 2014

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negative voltage across the PHASE and GND pins is nulled by the

while attempting to null the negative voltage across the PHASE

20µs has elapsed, the timer will be reset. An SCP fault will occur

Where:

setpoint

ISEN pin

that will activate the OCP circuit

Overvoltage Protection

When an OVP fault is detected, the PGOOD pin will pull down to

The OVP fault detection circuit triggers after the voltage across

the FB and GND pins has increased above the rising overvoltage

response to an OVP fault, the LG gate-driver output will retain the

ability to toggle the low-side MOSFET on and off, in response to

Undervoltage Protection

When a UVP fault is detected, the PGOOD pin will pull down to

until the EN pin has been pulled below the falling EN threshold

triggers after the voltage across the FB and GND pins has fallen

Over-Temperature

When the temperature of the ISL6269A increases above the

that suspends the PWM , forcing the LG and UG gate-driver

outputs low. The status of the PGOOD pin does not change nor

does the converter latch-off. The PWM remains suspended until

the IC temperature falls below the hysteresis temperature

state can be reset if the EN pin is pulled below the falling EN

normally during OTP. It is likely that the IC will detect an UVP fault

because in the absence of PWM, the output voltage immediately

remain latched until the EN pin has been pulled below the falling

Programming the Output Voltage

When the converter is in regulation there will be 600mV from the

FB pin to the GND pin. Connect a two-resistor voltage divider

across the VO pin and the GND pin with the output node

connected to the FB pin. Scale the voltage-divider network such

that the FB pin is 600mV with respect to the GND pin when the

converter is regulating at the desired output voltage. The output

voltage can be programmed from 600mV to 3.3V.

Programming the output voltage is written as:

Where:

the FB pin and the GND pin

from the FB pin to the VO pin. In addition to setting the

output voltage, this resistor is part of the loop compensation

network

from the FB pin to the GND pin

is written as:

Programming the PWM Switching Frequency

The ISL6269A does not use a clock signal to produce PWM. The

approximate PWM switching frequency is written as:

Where:

It is recommended that whenever the control loop compensation

I



I





=

(EQ. 3)

(EQ. 4)

R

SEN

I

FL

I

P-P

2

----------

+





OC

SP



r

DS ON





I

OC

------------------------------------------------------------------------------

=

V

REF

V

OUT

R

BOTTOM

R

TOP

R

BOTTOM

+

---------------------------------------------------



=

(EQ. 5)

R

BOTTOM

V



TOP

V

OUT

V

REF

–

-------------------------------------

=

(EQ. 6)

f

SW

1

KR

FSET



---------------------------

=

(EQ. 7)

R

FSET

1

Kf

SW



------------------

=

(EQ. 8)