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66AK2L06XCMSA2 Datasheet(PDF) 11 Page - Texas Instruments |
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66AK2L06XCMSA2 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 298 page  Boot Controller LPSC PLLC GPSC .L1 .S1 .M1 xx xx .D1 .D2 .M2 xx xx .S2 .L2 Data Memory Controller (DMC) With Memory Protect/Bandwidth Mgmt 32KB L1D CFG Switch Fabric DMA Switch Fabric Data Path A A Register File A31-A16 A15-A0 Data Path B B Register File B31-B16 B15-B0 C66x DSP Core Instruction Fetch 16-/32-bit Instruction Dispatch Control Registers In-Circuit Emulation Instruction Decode 32KB L1P Memory Controller (PMC) With Memory Protect/Bandwidth Mgmt L2 Cache/ SRAM 1024KB RSA MSM SRAM 2048KB DDR3 SRAM RSA 66AK2L0x 66AK2L06 www.ti.com SPRS930 – APRIL 2015 4 C66x CorePac The C66x CorePac consists of several components: • Level-one and level-two memories (L1P, L1D, L2) • Data Trace Formatter (DTF) • Embedded Trace Buffer (ETB) • Interrupt controller • Power-down controller • External memory controller • Extended memory controller • A dedicated local power/sleep controller (LPSC) The C66x CorePac also provides support for big and little endianness, memory protection, and bandwidth management (for resources local to the CorePac). Figure 4-1 shows a block diagram of the C66x CorePac. Figure 4-1. C66x CorePac Block Diagram For more detailed information on the C66x CorePac in the 66AK2L06 device, see theTMS320C66x DSP CorePac User's Guide (SPRUGW0). Copyright © 2015, Texas Instruments Incorporated C66x CorePac 11 Submit Documentation Feedback Product Folder Links: 66AK2L06 |
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