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TAS5404-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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TAS5404-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 47 page  TAS5404-Q1 www.ti.com SLOS918A – AUGUST 2015 – REVISED OCTOBER 2015 7.5 Electrical Characteristics Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ, AES17 filter, default I 2C settings, master-mode operation (see Figure 20) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING CURRENT IPVDD_IDLE All four channels in MUTE mode 170 220 PVDD idle current mA IPVDD_Hi-Z All four channels in Hi-Z mode 93 IPVDD_STBY PVDD standby current STANDBY mode, TJ ≤ 85°C 2 10 μA OUTPUT POWER 4 Ω, THD+N ≤ 1%, 1 kHz, Tc = 75°C 20 4 Ω, THD+N = 10%, 1 kHz, Tc = 75°C 25 26 4 Ω, square wave, 1 kHz, Tc = 75°C 43 POUT Output power per channel W 2 Ω, THD+N = 1%, 1 kHz, Tc = 75°C 38 2 Ω, THD+N = 10%, 1 kHz, Tc = 75°C 40 45 2 Ω, square wave, 1 kHz, Tc = 75°C 70 4 channels operating, 20-W output power/ch, L = 10 μH, EFFP Power efficiency 90% TJ ≤ 85°C AUDIO PERFORMANCE VNOISE Noise voltage at output Zero input, and A-weighting 60 100 μV P = 1 W, f = 1 kHz, enhanced crosstalk enabled through Channel crosstalk 70 85 dB I2C (reg. 0x10) Common-mode rejection ratio (TAS5424C- CMRR5424 f = 1 kHz, 1 Vrms referenced to GND, G = 26 dB 60 75 dB Q1) PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 60 75 dB THD+N Total harmonic distortion + noise P = 1 W, f = 1 kHz 0.02% 0.1% 336 357 378 Switching frequency selectable for AM interference fS Switching frequency 392 417 442 kHz avoidance 470 500 530 RAIN Analog input resistance Internal shunt resistance on each input pin 63 85 106 k Ω AC-coupled common-mode input voltage (zero VIN_CM Common-mode input voltage 1.3 Vrms differential input) VCM_INT Internal common-mode input bias voltage Internal bias applied to IN_M pin 3.3 V 11 12 13 19 20 21 Source impedance = 0 Ω, gain measurement taken at 1 G Voltage gain (VO/VIN) dB W of power per channel 25 26 27 31 32 33 GCH Channel-to-channel variation Any gain commanded –1 0 1 dB PWM OUTPUT STAGE RDS(on) FET drain-to-source resistance Not including bond wire resistance, TJ = 25°C 65 90 m Ω VO_OFFSET Output offset voltage Zero input signal, G = 26 dB ±10 ±50 mV PVDD OVERVOLTAGE (OV) PROTECTION VOV_SET PVDD overvoltage shutdown set 24.6 26.4 28.2 V VOV_CLEAR PVDD overvoltage shutdown clear 24.4 25.9 27.4 V PVDD UNDERVOLTAGE (UV) PROTECTION VUV_SET PVDD undervoltage shutdown set 4.9 5.3 5.5 V VUV_CLEAR PVDD undervoltage shutdown clear 6.2 6.6 6.9 V AVDD VA_BYP A_BYP pin voltage 6.5 V VA_BYP_UV_SET A_BYP UV voltage 4.8 V VA_BYP_UV_CLEAR Recovery voltage A_BYP UV 5.3 V DVDD VD_BYP D_BYP pin voltage 3.3 V POWER-ON RESET (POR) VPOR PVDD voltage for POR 4 V I2C active above this voltage VPOR_HY PVDD recovery hysteresis voltage for POR 0.1 V Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TAS5404-Q1 |
Similar Part No. - TAS5404-Q1_15 |
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Similar Description - TAS5404-Q1_15 |
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