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ISL6622ACBZ Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL6622ACBZ Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 11 page 5 FN6601.2 March 19, 2009 Three-State Upper Gate Rising Threshold (Note 4) VCC = 12V - 3.2 - V Three-State Upper Gate Falling Threshold (Note 4) VCC = 12V - 2.8 - V UGATE Rise Time (Note 4) tRU VVCC = 12V, 3nF Load, 10% to 90% - 26 - ns LGATE Rise Time (Note 4) tRL VVCC = 12V, 3nF Load, 10% to 90% - 18 - ns UGATE Fall Time (Note 4) tFU VVCC = 12V, 3nF Load, 90% to 10% - 18 - ns LGATE Fall Time (Note 4) tFL VVCC = 12V, 3nF Load, 90% to 10% - 12 - ns UGATE Turn-On Propagation Delay (Note 4) tPDHU VVCC = 12V, 3nF Load, Adaptive - 20 - ns LGATE Turn-On Propagation Delay (Note 4) tPDHL VVCC = 12V, 3nF Load, Adaptive - 10 - ns UGATE Turn-Off Propagation Delay (Note 4) tPDLU VVCC = 12V, 3nF Load - 10 - ns LGATE Turn-Off Propagation Delay (Note 4) tPDLL VVCC = 12V, 3nF Load - 10 - ns LG/UG Three-State Propagation Delay (Note 4) tPDTS VVCC = 12V, 3nF Load - 10 - ns Diode Braking Holdoff Time (Note 4) tUG_OFF_DB VVCC = 12V - 60 - ns Minimum LGATE On-Time at Diode Emulation tLG_ON_DM VVCC = 12V 230 330 450 ns OUTPUT (Note 4) Upper Drive Source Current IU_SOURCE VVCC = 12V, 3nF Load - 1.25 - A Upper Drive Source Impedance RU_SOURCE 20mA Source Current - 2 - Ω Upper Drive Sink Current IU_SINK VVCC = 12V, 3nF Load - 2 - A Upper Drive Sink Impedance RU_SINK 20mA Sink Current - 1.35 - Ω Lower Drive Source Current IL_SOURCE VVCC = 12V, 3nF Load - 2 - A Lower Drive Source Impedance RL_SOURCE 20mA Source Current - 1.35 - Ω Lower Drive Sink Current IL_SINK VVCC = 12V, 3nF Load - 3 - A Lower Drive Sink Impedance RL_SINK 20mA Sink Current - 0.9 - Ω Electrical Specifications Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Functional Pin Descriptions PACKAGE PIN # PIN SYMBOL FUNCTION SOIC DFN 1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET. 2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap Device” on page 7 for guidance in choosing the capacitor value. - 3 NC No Connect 3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation; see “Description” on page 6 for further details. Connect this pin to the PWM output of the controller. 4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver. 5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET. 6 7 LVCC This pin supplies power to the lower gate drive. Its operating range is +5V to +12V. Place a high quality low ESR ceramic capacitor from this pin to GND. - 8 UVCC This pin supplies power to the upper gate drive. Its operating range is +5V to +12V. Place a high quality low ESR ceramic capacitor from this pin to GND. 7 9 VCC Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC. Place a high quality low ESR ceramic capacitor from this pin to GND. 8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a return path for the upper gate drive. - 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection. ISL6622A |
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